Aldec

Aldec, Inc. is a privately owned electronic design automation company based in Henderson, Nevada, providing software and hardware used in creation and verification of digital designs targeting FPGA and ASIC technologies. As a member of Accellera and IEEE Standards Association, Aldec actively participates in the process of developing new standards and updating existing standards (e.g. VHDL, SystemVerilog). Aldec provides a hardware description language (HDL) simulation engine for other EDA tools such as Altium Designer and bundles special version of its tools with FPGA vendors software such as Lattice.

Aldec, Inc. is a privately owned electronic design automation company based in Henderson, Nevada, providing software and hardware used in creation and verification of digital designs targeting FPGA and ASIC technologies. As a member of Accellera and IEEE Standards Association, Aldec actively participates in the process of developing new standards and updating existing standards (e.g. VHDL, SystemVerilog). Aldec provides a hardware description language (HDL) simulation engine for other EDA tools such as Altium Designer and bundles special version of its tools with FPGA vendors software such as Lattice. === 2000-2024=== In 2000 Aldec released a high-performance HDL simulator working not only on Windows, but also on Solaris and Linux platforms. In 2001 ALDEC added hardware to its product line: the HES (Hardware Embedded Simulation) Platform allowing hardware acceleration of HDL simulation and incremental prototyping of hardware. 2003 marked the release of Riviera-PRO supporting assertion based verification (OpenVera, PSL and SystemVerilog can be used to write properties, assertions and coverage). Support for SystemC and non-assertion part of SystemVerilog was added in 2004. Interfaces to MATLAB and Simulink appeared in Aldec tools for the first time in 2005. In 2006 Riviera-PRO was the first simulator supporting Open IP Encryption Initiative by Synplicity. Stimulated by requests from Verilog users, Aldec released in 2007¹ an advanced, user-configurable lint tool implementing rules created by STJapanese consortium of major silicon vendors. In 2008, the company released ALINT: Design Rule Checker (STARC – Japanese Consortium of 11 ASIC Companies). In 2010, it released support for VHDL IEEE 1076¹-2008. Also in 2010, Aldec's Active-HDL won the Best FPGA Design & Simulation Tool in China. In 2011, Aldec delivered UVM 1.0, OVM 2.1.2 and VMM 1.1.1a support, and released a 4 MHz Design Emulator. It also won Best FPGA Design & Verification Platform Provider in China. In 2012, Aldec entered the SoC/ASIC prototyping market with HES-7, and jointly launched OSVVM and VHDL Verification. In 2013, Aldec released Spec-TRACER Requirements Lifecycle Management. In 2015, Aldec released ALINT-PRO with CDC Verification, and in 2016¹, Aldec released TySOM Product Line for Embedded Development using SoC FPGAs. In 2020, it released support for VHDL IEEE 1076-2019.

Text derived from https://en.wikipedia.org/w/index.php?oldid=1375804130 under CC BY-SA 4.0; modifications have been made.