Current mirror

A current mirror is a circuit designed to copy a current through one active device by controlling the current in another active device of a circuit, keeping the output current constant regardless of loading. The current being "copied" can be, and sometimes is, a varying signal current. Conceptually, an ideal current mirror is simply an ideal inverting current amplifier that reverses the current direction as well, or it could consist of a current-controlled current source (CCCS). The current mirror is used to provide bias currents and active loads to circuits. It can also be used to model a more realistic current source (since ideal current sources do not exist). The circuit topology covered here is one that appears in many monolithic integrated circuits (ICs). It is a Widlar mirror without an emitter degeneration resistor in the follower (output) transistor. This topology can only be done in an IC, as the matching has to be extremely close and cannot be achieved with discretes. Another topology is the Wilson current mirror. The Wilson mirror solves the Early effect voltage problem in this design. Current mirrors are applied in both analog and mixed VLSI circuits.

A current mirror is a circuit designed to copy a current through one active device by controlling the current in another active device of a circuit, keeping the output current constant regardless of loading. The current being "copied" can be, and sometimes is, a varying signal current. Conceptually, an ideal current mirror is simply an ideal inverting current amplifier that reverses the current direction as well, or it could consist of a current-controlled current source (CCCS). The current mirror is used to provide bias currents and active loads to circuits. It can also be used to model a more realistic current source (since ideal current sources do not exist). The circuit topology covered here is one that appears in many monolithic integrated circuits (ICs). It is a Widlar mirror without an emitter degeneration resistor in the follower (output) transistor. This topology can only be done in an IC, as the matching has to be extremely close and cannot be achieved with discretes. Another topology is the Wilson current mirror. The Wilson mirror solves the Early effect voltage problem in this design. Current mirrors are applied in both analog and mixed VLSI circuits. I_\text{C} = I_\text{S} \left( e^{\frac{V_\text{BE}}{V_\text{T}}} - 1 \right) \left(1 + \frac{V_\text{CE}}{V_\text{A}}\right), where I S is the reverse saturation current or scale current; V T , the thermal voltage; and V A , the Early voltage. This current is related to the reference current I ref when the output transistor V CB = 0 V by: I_\text{ref} = I_C \left( 1 + \frac{2}{\beta_0} \right), as found using Kirchhoff's current law at the collector node of Q 1 : I_\text{ref} = I_C + I_{B1} + I_{B2} \ . The reference current supplies the collector current to Q 1 and the base currents to both transistors – when both transistors have zero base-collector bias, the two base currents are equal, I B1 = I B2 = I B . I_\text{ref} = I_C + I_B + I_B = I_C + 2 I_B = I_C \left(1 + \frac {2} {\beta_0} \right), Parameter β 0 is the transistor β-value for V CB = 0 V. R_N = r_o = \frac{V_A + V_{CE}}{I_C} \ , where V A is the Early voltage; and V CE , the collector-to-emitter voltage of output transistor. To keep the output transistor active, V CB ≥ 0 V. That means the lowest output voltage that results in correct mirror behavior, the compliance voltage, is V OUT = V CV = V BE under bias conditions with the output transistor at the output current level I C and with V CB = 0 V or, inverting the I–V relation above: V_{CV} = V_T \ln\left(\frac{I_C}{I_S} + 1\right), where V T is the thermal voltage; and I S , the reverse saturation current or scale current. \beta_1 &= \beta_0 \\ \beta_2 &= \beta_0 \left(1 + \frac{V_{CB}}{V_A}\right), \end{align} where V A is the Early voltage and β 0 is the transistor β for V CB = 0 V. Besides the difference due to the Early effect, the transistor β-values will differ because the β 0 -values depend on current, and the two transistors now carry different currents (see Gummel–Poon model). Further, Q 2 may get substantially hotter than Q 1 due to the associated higher power dissipation. To maintain matching, the temperature of the transistors must be nearly the same. In integrated circuits and transistor arrays where both transistors are on the same die, this is easy to achieve. But if the two transistors are widely separated, the precision of the current mirror is compromised. Additional matched transistors can be connected to the same base and will supply the same collector current. In other words, the right half of the circuit can be duplicated several times. Note, however, that each additional right-half transistor "steals" a bit of collector current from Q 1 due to the non-zero base currents of the right-half transistors. This will result in a small reduction in the programmed current. See also an example of a mirror with emitter degeneration to increase mirror resistance. For the simple mirror shown in the diagram, typical values of \beta will yield a current match of 1% or better. The drain current of a MOSFET I D is a function of both the gate-source voltage and the drain-to-gate voltage of the MOSFET given by I D = (V GS , V DG ), a relationship derived from the functionality of the MOSFET device. In the case of transistor M 1 of the mirror, I D = I REF . Reference current I REF is a known current, and can be provided by a resistor as shown, or by a "threshold-referenced" or "self-biased" current source to ensure that it is constant, independent of voltage supply variations. Using V DG = 0 for transistor M 1 , the drain current in M 1 is I D = (V GS , V DG =0), so we find: (V GS , 0) = I REF , implicitly determining the value of V GS . Thus I REF sets the value of V GS . The circuit in the diagram forces the same V GS to apply to transistor M 2 . If M 2 is also biased with zero V DG and provided transistors M 1 and M 2 have good matching of their properties, such as channel length, width, threshold voltage, etc., the relationship I OUT = (V GS , V DG = 0) applies, thus setting I OUT = I REF ; that is, the output current is the same as the reference current when V DG = 0 for the output transistor, and both transistors are matched. The drain-to-source voltage can be expressed as V DS = V DG + V GS . With this substitution, the Shichman–Hodges model provides an approximate form for function (V GS , V DG ): \begin{align} I_\text{d} &= f(V_\text{GS}, V_\text{DG}) \\ &= \frac{1}{2} K_\text{p} \left(\frac{W}{L}\right)\left(V_\text{GS} - V_\text{th}\right)^2 \left(1 + \lambda V_\text{DS}\right) \\ &= \frac{1}{2} K_\text{p} \left[\frac{W}{L}\right]\left[V_\text{GS} - V_\text{th}\right]^2 \left[1 + \lambda (V_\text{DG} + V_\text{GS})\right] , \\ \end{align} where K_\text{p} is a technology-related constant associated with the transistor, W/L is the width to length ratio of the transistor, V_\text{GS} is the gate-source voltage, V_\text{th} is the threshold voltage, λ is the channel length modulation constant, and V_{DS} is the drain-source voltage. R_\text{N} = r_\text{o} = \frac{1}{I_\text{D}}\left(\frac{1}{\lambda}r + V_\text{DS}\right) = \frac{1}{I_\text{D}}\left(V_\text{E} L + V_\text{DS}\right), where λ = channel-length modulation parameter and V DS is the drain-to-source bias. To keep the output transistor resistance high, V DG ≥ 0 V. (see Baker). That means the lowest output voltage that results in correct mirror behavior, the compliance voltage, is V OUT = V CV = V GS for the output transistor at the output current level with V DG = 0 V, or using the inverse of the f-function, −1 : V_\text{CV} = V_\text{GS} (\text{for}\ I_\text{D}\ \text{at} \ V_\text{DG} = 0V) = f^{-1}(I_\text{D}) \ \text{with}\ V_\text{DG} = 0 \ . For the Shichman–Hodges model, −1 is approximately a square-root function. V_1 - V_2 = \frac{V_B}{A_v}. Consequently, the currents in the two leg resistors are held nearly the same, and the output current of the mirror is very nearly the same as the collector current I C1 in Q 1 , which in turn is set by the reference current as I_\text{ref} = I_{C1} \left(1 + \frac{1}{\beta_1}\right), where β 1 for transistor Q 1 and β 2 for Q 2 differ due to the Early effect if the reverse bias across the collector-base of Q 2 is non-zero. ; a test current I X at the output generates a voltage V X , and the output resistance is R out = V X / I X . An idealized treatment of output resistance is given in the footnote. A small-signal analysis for an op amp with finite gain A v but otherwise ideal is based upon Figure 5 (β, r O and r π refer to Q 2 ). To arrive at Figure 5, notice that the positive input of the op amp in Figure 3 is at AC ground, so the voltage input to the op amp is simply the AC emitter voltage V e applied to its negative input, resulting in a voltage output of −A v V e . Using Ohm's law across the input resistance r π determines the small-signal base current I b as: I_\text{b} = \frac{V_\text{e}}\frac{r_\pi}{A_\text{v} + 1} \ . Combining this result with Ohm's law for R_\text{E} , V_\text{e} can be eliminated, to find: I_\text{b} = I_\text{X} \frac{R_\text{E}}{ R_\text{E} + \frac{r_\pi}{A_\text{v} + 1} }. Kirchhoff's voltage law from the test source I X to the ground of R E provides: V_\text{X} = (I_\text{X} + \beta I_\text{b)} r_\text{O} + (I_\text{X} - I_\text{b} )R_\text{E}. Substituting for I b and collecting terms the output resistance R out is found to be: R_\text{out} = \frac{V_\text{X}}{I_\text{X}} = r_\text{O} \left( 1 + \beta \frac{R_\text{E}}{R_\text{E} + \frac{r_\pi}{A_\text{v} + 1}} \right) + R_\text{E} \|\frac{r_\pi}{A_\text{v} + 1}. For a large gain A v ≫ r π / R E the maximum output resistance obtained with this circuit is R_\text{out} = (\beta + 1)r_O, a substantial improvement over the basic mirror where R out = r O . The small-signal analysis of the MOSFET circuit of Figure 4 is obtained from the bipolar analysis by setting β = g m r π in the formula for R out and then letting r π → ∞. The result is R_\text{out} = r_\text{O} \left[1 + g_\text{m} R_\text{E}(A_\text{v} + 1)\right] + R_\text{E}. This time, R E is the resistance of the source-leg MOSFETs M 3 , M 4 . Unlike Figure 3, however, as A v is increased (holding R E fixed in value), R out continues to increase, and does not approach a limiting value at large A v .

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