Dataflow architecture
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Dataflow architecture is a dataflow-based computer architecture that directly contrasts the traditional von Neumann architecture or control flow architecture. Dataflow architectures have no program counter, in concept: the executability and execution of instructions is solely determined based on the availability of input arguments to the instructions, so that the order of instruction execution may be hard to predict. Although no commercially successful general-purpose computer hardware has used a dataflow architecture, it has been successfully implemented in specialized hardware such as in digital signal processing, network routing, graphics processing, telemetry, and more recently in data warehousing, and artificial intelligence (as: polymorphic dataflow Convolution Engine, structure-driven, dataflow scheduling ). It is also very relevant in many software architectures today including database engine designs and parallel computing frameworks. Synchronous dataflow architectures tune to match the workload presented by real-time data path applications such as wire speed packet forwarding. Dataflow architectures that are deterministic in nature enable programmers to manage complex tasks such as processor load balancing, synchronization and accesses to common resources.…
Dataflow architecture is a dataflow-based computer architecture that directly contrasts the traditional von Neumann architecture or control flow architecture. Dataflow architectures have no program counter, in concept: the executability and execution of instructions is solely determined based on the availability of input arguments to the instructions, so that the order of instruction execution may be hard to predict. Although no commercially successful general-purpose computer hardware has used a dataflow architecture, it has been successfully implemented in specialized hardware such as in digital signal processing, network routing, graphics processing, telemetry, and more recently in data warehousing, and artificial intelligence (as: polymorphic dataflow Convolution Engine, structure-driven, dataflow scheduling ). It is also very relevant in many software architectures today including database engine designs and parallel computing frameworks. Synchronous dataflow architectures tune to match the workload presented by real-time data path applications such as wire speed packet forwarding. Dataflow architectures that are deterministic in nature enable programmers to manage complex tasks such as processor load balancing, synchronization and accesses to common resources. Meanwhile, there is a clash of terminology, since the term dataflow is used for a subarea of parallel programming: for dataflow programming.
Historically
In contrast to the above, analog differential analyzers were based purely on hardware in the form of dataflow architecture, with the property that the programming and computations aren't performed by any set of instructions at all and that there usually weren't any memory based decisions made in such programs. The programming is solely based on the configuration by the physical interconnection of specialized computing elements, which basically creates a form of a passive dataflow architecture. In October 2024, NextSilicon officially announced the launch of its Maverick-2 accelerator, a dataflow chip meant for HPC workloads. Since its launch, NextSilicon has partnered with Sandia National Laboratories to install the chip in the Spectra supercomputer. In July 2025, the startup Efficient Computer was reported to have built a dataflow chip called Electron E1.
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