Delay calculation

Article summary

Delay calculation is the term used in integrated circuit design for the calculation of the gate delay of a single logic gate and the wires attached to it. By contrast, static timing analysis computes the delays of entire paths, using delay calculation to determine the delay of each gate and wire. There are many methods used for delay calculation for the gate itself. The choice depends primarily on the speed and accuracy required: :*Circuit simulators such as SPICE may be used. This is the most accurate, but slowest, method. :*Two dimensional tables are commonly used in applications such as logic synthesis, placement and routing. These tables take an output load and input slope and generate a circuit delay and output slope. The values of the tables are usually computed using circuit simulators in a procedure referred to as characterization or standard cell characterization. A common file format for storing the lookup tables is the Liberty format. :*A very simple model called the K-factor model is sometimes used. This approximates the delay as a constant plus k times the load capacitance. :*A more complex model called Delay Calculation Language, or DCL, calls a user-defined program whenever a delay value is required. This allows arbitrarily complex models to be represented, but raises significant software engineering issues.…

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