Gem5

The gem5 simulator is an open-source discrete-event computer architecture simulator used for computer-system and microarchitectural research. It is widely used in academic and industrial computer-architecture research. gem5 models components of computer systems, including processors and memory hierarchies, allowing researchers to evaluate hardware configurations and architectural designs in software. gem5 supports both full-system simulation, in which a complete operating system runs on the simulated hardware, and syscall-emulation mode, in which user-space programs run without a simulated operating-system kernel. It supports several instruction set architectures (ISAs), including x86, Arm, RISC-V, MIPS, SPARC, and Power, as well as a range of processor and memory-system models. Simulated systems are configured primarily through Python, while most of the simulator itself is implemented in C++.

The gem5 simulator is an open-source discrete-event computer architecture simulator used for computer-system and microarchitectural research. It is widely used in academic and industrial computer-architecture research. gem5 models components of computer systems, including processors and memory hierarchies, allowing researchers to evaluate hardware configurations and architectural designs in software. gem5 supports both full-system simulation, in which a complete operating system runs on the simulated hardware, and syscall-emulation mode, in which user-space programs run without a simulated operating-system kernel. It supports several instruction set architectures (ISAs), including x86, Arm, RISC-V, MIPS, SPARC, and Power, as well as a range of processor and memory-system models. Simulated systems are configured primarily through Python, while most of the simulator itself is implemented in C++.

Text derived from https://en.wikipedia.org/w/index.php?oldid=1375604817 under CC BY-SA 4.0; modifications have been made.