I2S

Inter-Integrated Circuit Sound (I²S, I2S or IIS) is a serial bus for transmitting two-channel, digital audio as pulse-code modulation (PCM) between integrated circuit (IC) components of an electronic device. An I²S bus separates clock and serial data signals, resulting in simpler receivers than those required for asynchronous communications systems that need to recover the clock from the data stream. Despite a similar name, I²S is unrelated to I²C.

Inter-Integrated Circuit Sound (I²S, I2S or IIS) is a serial bus for transmitting two-channel, digital audio as pulse-code modulation (PCM) between integrated circuit (IC) components of an electronic device. An I²S bus separates clock and serial data signals, resulting in simpler receivers than those required for asynchronous communications systems that need to recover the clock from the data stream. Despite a similar name, I²S is unrelated to I²C.

History

The protocol standard was introduced in 1986 by Philips Semiconductor (now NXP Semiconductors) and was first revised on June 5, 1996. The standard was last revised on February 17, 2022 and updated terms master and slave to controller and target. Word select (WS), a.k.a. left-right clock (LRCLK) or frame sync (FS). 0 = Left channel, 1 = Right channel Serial data (SD), a.k.a. SDATA, SDIN, SDOUT, DACDAT, ADCDAT The protocol may also include the following lines: Master clock (typically 256 x LRCLK); not part of the standard, but is commonly included for synchronizing the internal operation of the analog/digital converters A multiplexed data line for upload The bit clock pulses once for each discrete bit of data on the data lines. The bit clock frequency is the product of the sample rate, the number of bits per channel and the number of channels. So, for example, CD Audio with a sample frequency of 44.1 kHz, with 16 bits of precision and two channels (stereo) has a bit clock frequency of: 44.1 kHz × 16 × 2 = 1.4112 MHz The word select clock lets the device know whether channel 1 (WS = 0) or channel 2 (WS = 1) is currently being sent, because I²S allows two channels to be sent on the same data line. It is a 50% duty-cycle signal that has the same frequency as the sample frequency. For stereo material, the I²S specification states that the left audio is transmitted on the low cycle of the word select clock, and the right channel is transmitted on the high cycle. It is typically synchronized to the falling edge of the serial clock, as the data is latched on the rising edge. The word select clock changes one bit clock period before the MSB is transmitted. This enables, for example, the receiver to store the previous word and clear the input for the next. Data is signed, encoded as two's complement with the MSB (most significant bit) first. This allows the number of bits per frame to be arbitrary, with no negotiation required between transmitter and receiver.

See also

References

Text derived from https://en.wikipedia.org/w/index.php?oldid=1355038255 under CC BY-SA 4.0; modifications have been made.