Lesson plan

IC layout editor

An integrated circuit layout editor or IC layout editor is an electronic design automation software tool that allows a user to digitize the shapes and patterns that form an integrated circuit. Typically the view will include the components (usually as P cells), metal routing tracks, vias and electrical pins. Software of this type is similar to computer aided drafting software, but is specialized for the task of integrated circuit layout. The typical flow for the layout of analogue circuits might be : :1. The layout engineer receives the schematic from the designer in electrical form :2. Either the tool or the layout engineer creates a physical view of the circuit including all of the required components, wires, layers and pads. :3. The layout engineer positions the components to minimize both the area required and the negative effects of layout parasitics upon the circuit performance and also to allow efficient routing to components. :4. The layout engineer uses metal routing and other layers at times to connect all of the components, again taking care to avoid unwanted layout parasitics. :5. The layout engineer uses DRC and LVS checks to ensure that the circuit is both manufacturable and functional.…

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Article summary

An integrated circuit layout editor or IC layout editor is an electronic design automation software tool that allows a user to digitize the shapes and patterns that form an integrated circuit. Typically the view will include the components (usually as P cells), metal routing tracks, vias and electrical pins. Software of this type is similar to computer aided drafting software, but is specialized for the task of integrated circuit layout. The typical flow for the layout of analogue circuits might be : :1. The layout engineer receives the schematic from the designer in electrical form :2. Either the tool or the layout engineer creates a physical view of the circuit including all of the required components, wires, layers and pads. :3. The layout engineer positions the components to minimize both the area required and the negative effects of layout parasitics upon the circuit performance and also to allow efficient routing to components. :4. The layout engineer uses metal routing and other layers at times to connect all of the components, again taking care to avoid unwanted layout parasitics. :5. The layout engineer uses DRC and LVS checks to ensure that the circuit is both manufacturable and functional.…

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Discussion questions

  1. Summarise the article in your own words. Which single claim would you verify first, and why?
  2. Which claim in this article is most likely to be revised as the sources update? How would you check its current status?
  3. If two sources disagreed about one of these facts, what would you need in order to trust one over the other?

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Key claims and bibliography are generated from the same tracked claims and sources as the article page.