Instruction selection
≈ 2 min read
Names in other languages
No names in other languages are held for this entry yet.
Article bodies are English and are not machine-translated. A name in another language is not a translation of the article.
__NOTOC__ In computer science, instruction selection is the stage of a compiler backend that transforms its middle-level intermediate representation (IR) into a low-level IR. In a typical compiler, instruction selection precedes both instruction scheduling and register allocation; hence its output IR has an infinite set of pseudo-registers (often known as temporaries) and may still be – and typically is – subject to peephole optimization. Otherwise, it closely resembles the target machine code, bytecode, or assembly language. For example, for the following sequence of middle-level IR code t1 = a t2 = b t3 = t1 + t2 a = t3 b = t1 a good instruction sequence for the x86 architecture is MOV EAX, a XCHG EAX, b ADD a, EAX For a comprehensive survey on instruction selection, see.
__NOTOC__ In computer science, instruction selection is the stage of a compiler backend that transforms its middle-level intermediate representation (IR) into a low-level IR. In a typical compiler, instruction selection precedes both instruction scheduling and register allocation; hence its output IR has an infinite set of pseudo-registers (often known as temporaries) and may still be – and typically is – subject to peephole optimization. Otherwise, it closely resembles the target machine code, bytecode, or assembly language. For example, for the following sequence of middle-level IR code t1 = a t2 = b t3 = t1 + t2 a = t3 b = t1 a good instruction sequence for the x86 architecture is MOV EAX, a XCHG EAX, b ADD a, EAX For a comprehensive survey on instruction selection, see. ==References== ==External links== Alternative ways of supporting different generations of computer
Text derived from https://en.wikipedia.org/w/index.php?oldid=1374730341 under CC BY-SA 4.0; modifications have been made.