Lesson plan

Interface logic model

In electronics, the interface logic model (ILM) is a technique to model blocks in hierarchical VLSI implementation flow. It is a gate level model of a physical block where only the connections from the inputs to the first stage of flip-flops, and the connections from the last stage of flip-flops to the outputs are in the model, including the flip-flops and the clock tree driving these flip-flops. All other internal flip-flop to flip-flop paths are stripped out of the ILM. The advantage of ILM is that the entire path (clock to clock path) is visible at top level for interface nets, unlike traditional block-based hierarchical implementation flow. This gives better accuracy in analysis for interface nets at negligible additional memory and runtime overhead.

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Article summary

In electronics, the interface logic model (ILM) is a technique to model blocks in hierarchical VLSI implementation flow. It is a gate level model of a physical block where only the connections from the inputs to the first stage of flip-flops, and the connections from the last stage of flip-flops to the outputs are in the model, including the flip-flops and the clock tree driving these flip-flops. All other internal flip-flop to flip-flop paths are stripped out of the ILM. The advantage of ILM is that the entire path (clock to clock path) is visible at top level for interface nets, unlike traditional block-based hierarchical implementation flow. This gives better accuracy in analysis for interface nets at negligible additional memory and runtime overhead.

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Discussion questions

  1. Summarise the article in your own words. Which single claim would you verify first, and why?
  2. Which claim in this article is most likely to be revised as the sources update? How would you check its current status?
  3. If two sources disagreed about one of these facts, what would you need in order to trust one over the other?

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Key claims and bibliography are generated from the same tracked claims and sources as the article page.