Memory timings

Article summary

Memory timings or RAM timings describe the timing information of a memory module or the onboard LPDDRx. Due to the inherent qualities of VLSI and microelectronics, memory chips require time to fully execute commands. Executing commands too quickly will result in data corruption and results in system instability. With appropriate time between commands, memory modules/chips can be given the opportunity to fully switch transistors, charge capacitors and correctly signal back information to the memory controller. Because system performance depends on how fast memory can be used, this timing directly affects the performance of the system. The timing of modern synchronous dynamic random-access memory (SDRAM) is commonly indicated using four parameters: CL, T RCD , T RP , and T RAS in units of clock cycles; they are commonly written as four numbers separated with hyphens, e.g. 7-8-8-24. Variations include: * The fourth (t RAS ) is often omitted. * Or a fifth, the Command rate, is sometimes added (normally 2T or 1T, also written 2N, 1N or CR2). These parameters (as part of a larger whole) specify the clock latency of certain specific commands issued to a random access memory. Lower numbers imply a shorter wait between commands (as determined in clock cycles). The Intel systems also have Gear 2 (Gear type 0) and Gear 4 (Gear type 1).…

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