Lesson plan
Overlay control
In silicon wafer manufacturing overlay control is the control of pattern-to-pattern alignment necessary in the manufacture of silicon wafers. Silicon wafers are currently manufactured in a sequence of steps, each stage placing a pattern of material on the wafer; in this way transistors, contacts, etc., all made of different materials, are laid down. In order for the final device to function correctly, these separate patterns must be aligned correctly – for example contacts, lines and transistors must all line up. Overlay control has always played an important role in semiconductor manufacturing, helping to monitor layer-to-layer alignment on multi-layer device structures. Misalignment of any kind can cause short circuits and connection failures, which in turn impact fab yield and profit margins. Overlay control has become even more critical now because the combination of increasing pattern density and innovative techniques such as double patterning and 193 nm immersion lithography creates a novel set of pattern-based yield challenges at the 45 nm technology node and below. This combination causes error budgets to shrink below 30 percent of design rules, where existing overlay metrology solutions cannot meet total measurement uncertainty (TMU) requirements.…
Article summary
In silicon wafer manufacturing overlay control is the control of pattern-to-pattern alignment necessary in the manufacture of silicon wafers. Silicon wafers are currently manufactured in a sequence of steps, each stage placing a pattern of material on the wafer; in this way transistors, contacts, etc., all made of different materials, are laid down. In order for the final device to function correctly, these separate patterns must be aligned correctly – for example contacts, lines and transistors must all line up. Overlay control has always played an important role in semiconductor manufacturing, helping to monitor layer-to-layer alignment on multi-layer device structures. Misalignment of any kind can cause short circuits and connection failures, which in turn impact fab yield and profit margins. Overlay control has become even more critical now because the combination of increasing pattern density and innovative techniques such as double patterning and 193 nm immersion lithography creates a novel set of pattern-based yield challenges at the 45 nm technology node and below. This combination causes error budgets to shrink below 30 percent of design rules, where existing overlay metrology solutions cannot meet total measurement uncertainty (TMU) requirements.…
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Discussion questions
- Summarise the article in your own words. Which single claim would you verify first, and why?
- Which claim in this article is most likely to be revised as the sources update? How would you check its current status?
- If two sources disagreed about one of these facts, what would you need in order to trust one over the other?
Bibliography
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Key claims and bibliography are generated from the same tracked claims and sources as the article page.