Lesson plan
R2000 microprocessor
The R2000 is a 32-bit microprocessor chipset developed by MIPS Computer Systems that implemented the MIPS I instruction set architecture (ISA). Introduced in May 1986, it was one of the first commercial implementations of a RISC architecture, preceded only by the IBM RT PC. The R2000 competed with Digital Equipment Corporation (DEC) VAX minicomputers and with Motorola 68020 and Intel Corporation 80386 microprocessors. R2000 users included Ardent Computer, DEC, Silicon Graphics, Northern Telecom and MIPS's own Unix workstations. The "first confirmed customer" of the R2000 was Prime Computer. The chipset consisted of the R2000 microprocessor, R2010 floating-point accelerator, and four R2020 write buffer chips. The core R2000 chip executed all non-floating-point instructions with a simple short pipeline. This chip also controlled the external code and data caches, made of fast standard SRAM chips organized with direct indexing and one-cycle read latency. The R2000 chip contained a small translation lookaside buffer for mapping virtual memory addresses. The R2010 chip held the floating point registers, floating point data paths, and their longer simple pipeline. Writes to main memory DRAM took several cycles to fully complete, but the R2020 chips queued and completed up to 4 pending writes to main memory, allowing the R2000 core to proceed without stalling itself.…
Article summary
The R2000 is a 32-bit microprocessor chipset developed by MIPS Computer Systems that implemented the MIPS I instruction set architecture (ISA). Introduced in May 1986, it was one of the first commercial implementations of a RISC architecture, preceded only by the IBM RT PC. The R2000 competed with Digital Equipment Corporation (DEC) VAX minicomputers and with Motorola 68020 and Intel Corporation 80386 microprocessors. R2000 users included Ardent Computer, DEC, Silicon Graphics, Northern Telecom and MIPS's own Unix workstations. The "first confirmed customer" of the R2000 was Prime Computer. The chipset consisted of the R2000 microprocessor, R2010 floating-point accelerator, and four R2020 write buffer chips. The core R2000 chip executed all non-floating-point instructions with a simple short pipeline. This chip also controlled the external code and data caches, made of fast standard SRAM chips organized with direct indexing and one-cycle read latency. The R2000 chip contained a small translation lookaside buffer for mapping virtual memory addresses. The R2010 chip held the floating point registers, floating point data paths, and their longer simple pipeline. Writes to main memory DRAM took several cycles to fully complete, but the R2020 chips queued and completed up to 4 pending writes to main memory, allowing the R2000 core to proceed without stalling itself.…
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Discussion questions
- Summarise the article in your own words. Which single claim would you verify first, and why?
- Which claim in this article is most likely to be revised as the sources update? How would you check its current status?
- If two sources disagreed about one of these facts, what would you need in order to trust one over the other?
Bibliography
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Key claims and bibliography are generated from the same tracked claims and sources as the article page.