Lesson plan

Socket FM2

Socket FM2+ (FM2b, FM2r2) is a zero insertion force CPU socket designed by AMD for their desktop "Kaveri" APUs (Steamroller-based) and Godavari APUs (Steamroller-based) to connect to the motherboard. The FM2+ has a slightly different pin configuration to Socket FM2 with two additional pin sockets. Socket FM2+ APUs are not compatible with Socket FM2 motherboards due to the aforementioned additional pins. However, socket FM2 APUs such as "Richland" and "Trinity" are compatible with the FM2+ socket. * ECC DIMMs are supported on Socket FP3 but not supported on the Socket FM2+ package. * There are 3 PCI Express cores: one 2 ×16 core and two 5 ×8 cores. There are 8 configurable ports, which can be divided into 2 groups: ** Gfx-group: contains 2 ×8 ports. Each port can be limited to lower link widths for applications that require fewer lanes. Additionally, the two ports can be combined to create a single ×16 link. ** GPP-group: contains 1 ×4 UMI and 5 General Purpose Ports (GPP). All PCIe links are capable of supporting PCIe 2.0 data rates. In addition, the Gfx link is capable of supporting PCIe 3.x data rate. For available chipsets consult Fusion controller hubs (FCH). Its mobile counterpart is Socket FP3 (μBGA906).

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Article summary

Socket FM2+ (FM2b, FM2r2) is a zero insertion force CPU socket designed by AMD for their desktop "Kaveri" APUs (Steamroller-based) and Godavari APUs (Steamroller-based) to connect to the motherboard. The FM2+ has a slightly different pin configuration to Socket FM2 with two additional pin sockets. Socket FM2+ APUs are not compatible with Socket FM2 motherboards due to the aforementioned additional pins. However, socket FM2 APUs such as "Richland" and "Trinity" are compatible with the FM2+ socket. * ECC DIMMs are supported on Socket FP3 but not supported on the Socket FM2+ package. * There are 3 PCI Express cores: one 2 ×16 core and two 5 ×8 cores. There are 8 configurable ports, which can be divided into 2 groups: ** Gfx-group: contains 2 ×8 ports. Each port can be limited to lower link widths for applications that require fewer lanes. Additionally, the two ports can be combined to create a single ×16 link. ** GPP-group: contains 1 ×4 UMI and 5 General Purpose Ports (GPP). All PCIe links are capable of supporting PCIe 2.0 data rates. In addition, the Gfx link is capable of supporting PCIe 3.x data rate. For available chipsets consult Fusion controller hubs (FCH). Its mobile counterpart is Socket FP3 (μBGA906).

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  1. Summarise the article in your own words. Which single claim would you verify first, and why?
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  3. If two sources disagreed about one of these facts, what would you need in order to trust one over the other?

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