Strain engineering

Strain engineering refers to a general strategy employed in semiconductor manufacturing to enhance device performance. Performance benefits are achieved by modulating strain, as one example, in the transistor channel, which enhances electron mobility (or hole mobility) and thereby conductivity through the channel. Another example is semiconductor photocatalysts strain-engineered for more effective use of sunlight.

Strain engineering refers to a general strategy employed in semiconductor manufacturing to enhance device performance. Performance benefits are achieved by modulating strain, as one example, in the transistor channel, which enhances electron mobility (or hole mobility) and thereby conductivity through the channel. Another example is semiconductor photocatalysts strain-engineered for more effective use of sunlight. ==In CMOS manufacturing== The use of various strain engineering techniques has been reported by many prominent microprocessor manufacturers, including AMD, IBM, and Intel, primarily with regards to sub-130 nm technologies. One key consideration in using strain engineering in CMOS technologies is that PMOS and NMOS respond differently to different types of strain. Specifically, PMOS performance is best served by applying compressive strain to the channel, whereas NMOS receives benefit from tensile strain. Many approaches to strain engineering induce strain locally, allowing both n-channel and p-channel strain to be modulated independently. One prominent approach involves the use of a strain-inducing capping layer. CVD silicon nitride is a common choice for a strained capping layer, in that the magnitude and type of strain (e.g. tensile vs compressive) may be adjusted by modulating the deposition conditions, especially temperature. Standard lithography patterning techniques can be used to selectively deposit strain-inducing capping layers, to deposit a compressive film over only the PMOS, for example. Capping layers are key to the Dual Stress Liner (DSL) approach reported by IBM-AMD. In the DSL process, standard patterning and lithography techniques are used to selectively deposit a tensile silicon nitride film over the NMOS and a compressive silicon nitride film over the PMOS. A second prominent approach involves the use of a silicon-rich solid solution, especially silicon-germanium, to modulate channel strain. One manufacturing method involves epitaxial growth of silicon on top of a relaxed silicon-germanium underlayer. Tensile strain is induced in the silicon as the lattice of the silicon layer is stretched to mimic the larger lattice constant of the underlying silicon-germanium. Conversely, compressive strain could be induced by using a solid solution with a smaller lattice constant, such as silicon-carbon. See, e.g., U.S. Patent No. 7,023,018. Another closely related method involves replacing the source and drain region of a MOSFET with silicon-germanium. ==In thin films== Strain can be induced in thin films with either epitaxial growth, or more recently, topological growth. Epitaxial strain in thin films generally arises due to lattice mismatch between the film and its substrate and triple junction restructuring at the surface triple junction, which arises either during film growth or due to thermal expansion mismatch. Tuning this epitaxial strain can be used to moderate the properties of thin films and induce phase transitions. The misfit parameter ( f ) is given by the equation below: f=(a_s - a_e)/a_e where a_e is the lattice parameter of the epitaxial film and a_s is the lattice parameter of the substrate. After some critical film thickness, it becomes energetically favorable to relieve some mismatch strain through the formation of misfit dislocations or microtwins. Misfit dislocations can be interpreted as a dangling bond at an interface between layers with different lattice constants. This critical thickness ( h_c ) was computed by Mathews and Blakeslee to be: h_c = \frac{b(2-\nu cos^2\alpha)[ln(h_c/b)+1]}{8\pi |f|(1+\nu)cos\lambda} where b is the length of the Burgers vector, \nu is the Poisson ratio, \alpha is the angle between the Burgers vector and misfit dislocation line, and \lambda is the angle between the Burgers vector and the vector normal to the dislocation's glide plane. The equilibrium in-plane strain for a thin film with a thickness ( h ) that exceeds h_c is then given by the expression: \epsilon_ = \frac{f} \frac{b(1-\nu cos^2(\alpha)[ln(h/b) +1]}{8\pi |f| (1+\nu)cos\lambda} Strain relaxation at thin film interfaces via misfit dislocation nucleation and multiplication occurs in three stages which are distinguishable based on the relaxation rate. The first stage is dominated by glide of pre-existing dislocations and is characterized by a slow relaxation rate. The second stage has a faster relaxation rate, which depends on the mechanisms for dislocation nucleation in the material. Finally, the last stage represents a saturation in strain relaxation due to strain hardening. Strain engineering has been well-studied in complex oxide systems, in which epitaxial strain can strongly influence the coupling between the spin, charge, and orbital degrees of freedom, and thereby impact the electrical and magnetic properties. Epitaxial strain has been shown to induce metal-insulator transitions and shift the Curie temperature for the antiferromagnetic-to-ferromagnetic transition in La_{1-x}Sr_{x}MnO_{3} . In alloy thin films, epitaxial strain has been observed to impact the spinodal instability, and therefore impact the driving force for phase separation. This is explained as a coupling between the imposed epitaxial strain and the system's composition-dependent elastic properties. Researchers more recently have achieved strain in thick oxide films larger than that achieved in epitaxial growth by incorporating nano-structured topologies (Guerra and Vezenov, 2002) and nanorods/nanopillars within an oxide film matrix. Following this work, researchers world-wide have created such self-organized, phase-separated, nanorod/nanopillar structures in numerous oxide films as reviewed here. In 2008, Thulin and Guerra published calculations of strain-modified anatase titania band structures, which included an indicated higher hole mobility with increasing strain. Additionally, in two dimensional materials such as strain has been shown to induce conversion from an indirect semiconductor to a direct semiconductor allowing a hundred-fold increase in the light emission rate. ==In III-N LEDs== Strain engineering plays a major role in III-N LEDs, one of the most ubiquitous and efficient LED varieties that has only gained popularity after the 2014 Nobel Prize in Physics. Most III-N LEDs utilize a combination of GaN and InGaN, the latter being used as the quantum well region. The composition of In within the InGaN layer can be tuned to change the color of the light emitted from these LEDs. However, the epilayers of the LED quantum well have inherently mismatched lattice constants, creating strain between the layers. Due to the quantum confined Stark effect (QCSE), the electron and hole wave functions are misaligned within the quantum well, resulting in a reduced overlap integral, decreased recombination probability, and increased carrier lifetime. As such, applying an external strain can negate the internal quantum well strain, reducing the carrier lifetime and making the LEDs a more attractive light source for communications and other applications requiring fast modulation speeds. With appropriate strain engineering, it is possible to grow III-N LEDs on Si substrates. This can be accomplished via strain relaxed templates, superlattices, and pseudo-substrates. Furthermore, electro-plated metal substrates have also shown promise in applying an external counterbalancing strain to increase the overall LED efficiency. ===In DUV LEDs=== In addition to traditional strain engineering that takes place with III-N LEDs, Deep Ultraviolet (DUV) LEDs, which use AlN, AlGaN, and GaN, undergo a polarity switch from TE to TM at a critical Al composition within the active region. The polarity switch arises from the negative value of AlN's crystal field splitting, which results in its valence bands switching character at this critical Al composition. Studies have established a linear relationship between this critical composition within the active layer and the Al composition used in the substrate templating region, underscoring the importance of strain engineering in the character of light emitted from DUV LEDs. Furthermore, any existing lattice mismatch causes phase separation and surface roughness, in addition to creating dislocations and point defects. The former results in local current leakage while the latter enhances the nonradiative recombination process, both reducing the device's internal quantum efficiency (IQE). Active layer thickness can trigger the bending and annihilation of threading dislocations, surface roughening, phase separation, misfit dislocation formation, and point defects. All of these mechanisms compete across different thicknesses. By delaying strain accumulation to grow at a thicker epilayer before reaching the target relaxation degree, certain adverse effects can be reduced. ==See also== Strained silicon ==References==

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