Titan (processor)

Uses your system voice; voice and rate in settings.

Snapshot

≈ 2 min read

Names in other languages

No names in other languages are held for this entry yet.

Article bodies are English and are not machine-translated. A name in another language is not a translation of the article.

Titan was a planned family of 32-bit Power ISA-based microprocessor cores designed by Applied Micro Circuits Corporation (AMCC), but was scrapped in 2010. Applied Micro chose to continue development of the PowerPC 400 core instead, on a 40 nm fabrication process.

Titan was a planned family of 32-bit Power ISA-based microprocessor cores designed by Applied Micro Circuits Corporation (AMCC), but was scrapped in 2010. Applied Micro chose to continue development of the PowerPC 400 core instead, on a 40 nm fabrication process. ==Details== It was designed to be the foundation of embedded processors and system-on-a-chip (SoC) solutions. While being high performance, reaching speeds up to 2 GHz, it would remain extremely power efficient, drawing just 2.5 W per core. Where there usually is a trade-off between performance and power, AMCC used the Fast14 technology from Intrinsity to build an extremely efficient microprocessor design leveraging high performance combined with low power and comparably cheap bulk 90 nm CMOS manufacturing. By using NMOS transistors and no latches, the design results in a chip with fewer transistors than traditional design, thus reducing cost. The design allows for dual core SoC implementations consuming less than 15 W. There were plans for single, dual and quad-core versions. The Titan had a new superscalar, out of order 8-9 stage core with a novel three-stage CPU cache design. Small 4/4 KiB instruction and data caches at "level 0" sit before the traditional 32/32 KiB L1 caches up to 1 MB L2 cache that will be shared between all cores (supporting up to four). The Titan was compliant with the Power ISA v.2.04. APM 83290 – The first implementations of the Titan core design, codenamed Gemini. Two 1.5 GHz cores with FPU, 512 kB shared L2 cache, DDR2 controller, security engine, multi-channel DMA and I/O engine for gigabit Ethernet, PCIe, USB, RapidIO and SATA. It began sampling in October 2009 The processor is aimed at telecom and control plane applications. It is built using TSMC's 90 nm bulk CMOS fabrication to reduce cost.[http://investor.appliedmicro.com/phoenix.zhtml?c=78121&p=irol-newsArticle&ID=1342823 ==References== AMCC's pressrelease AMCC Next Generation Power Architecture Processor – Titan – Power.org AMCC drives to high end of embedded PowerPC market – EETimes Intrinsity Nets 2 GHz, 4000 DMIPS PowerPC FastCore – Market Wire

Text derived from https://en.wikipedia.org/w/index.php?oldid=1231604317 under CC BY-SA 4.0; modifications have been made.

Provenance

snapshot enwiki-001231604317 · captured 1719634991.0 · version history

Cite this page as: encyclopegia.org, “Titan (processor)”, snapshot enwiki-001231604317. https://encyclopegia.org/a/titan-processor