Electron E1
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The Electron E1 is a power efficient CPU designed by Efficient Computer with an innovative architecture. Instead of the von Neumann architecture, the chip uses compute nodes distributed across the area of the chip. Rather than sequentially executed instructions, a compiled program is spatially distributed, with data flowing between the different instruction nodes when the results are ready rather than sequentially executed. Compared to systolic arrays or digital signal processors, the data flow is more flexible. Efficiency is improved since there is no instruction fetching, data caching, or collision detection.
The Electron E1 is a power efficient CPU designed by Efficient Computer with an innovative architecture. Instead of the von Neumann architecture, the chip uses compute nodes distributed across the area of the chip. Rather than sequentially executed instructions, a compiled program is spatially distributed, with data flowing between the different instruction nodes when the results are ready rather than sequentially executed. Compared to systolic arrays or digital signal processors, the data flow is more flexible. Efficiency is improved since there is no instruction fetching, data caching, or collision detection. ==References==
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