Lesson plan

Memory controller

A memory controller, also known as memory chip controller (MCC) or a memory controller unit (MCU), is a digital circuit that manages the flow of data going to and from a computer's main memory. When a memory controller is integrated into another chip, such as an integral part of a microprocessor, it is usually called an integrated memory controller (IMC). Memory controllers contain the logic necessary to read and write dynamic random-access memory (DRAM), and to provide the critical memory refresh and other functions. Reading and writing to DRAM is performed by selecting the row and column data addresses of the DRAM as the inputs to the multiplexer circuit, where the demultiplexer on the DRAM uses the converted inputs to select the correct memory location and return the data, which is then passed back through a multiplexer to consolidate the data in order to reduce the required bus width for the operation. Memory controllers' bus widths range from 8-bit in earlier systems, to 512-bit in more complicated systems, where they are typically implemented as four 64-bit simultaneous memory controllers operating in parallel, though some operate with two 64-bit memory controllers being used to access a 128-bit memory device. Some memory controllers, such as the one integrated into PowerQUICC II processors, include error detection and correction hardware.…

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Article summary

A memory controller, also known as memory chip controller (MCC) or a memory controller unit (MCU), is a digital circuit that manages the flow of data going to and from a computer's main memory. When a memory controller is integrated into another chip, such as an integral part of a microprocessor, it is usually called an integrated memory controller (IMC). Memory controllers contain the logic necessary to read and write dynamic random-access memory (DRAM), and to provide the critical memory refresh and other functions. Reading and writing to DRAM is performed by selecting the row and column data addresses of the DRAM as the inputs to the multiplexer circuit, where the demultiplexer on the DRAM uses the converted inputs to select the correct memory location and return the data, which is then passed back through a multiplexer to consolidate the data in order to reduce the required bus width for the operation. Memory controllers' bus widths range from 8-bit in earlier systems, to 512-bit in more complicated systems, where they are typically implemented as four 64-bit simultaneous memory controllers operating in parallel, though some operate with two 64-bit memory controllers being used to access a 128-bit memory device. Some memory controllers, such as the one integrated into PowerQUICC II processors, include error detection and correction hardware.…

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  1. Summarise the article in your own words. Which single claim would you verify first, and why?
  2. Which claim in this article is most likely to be revised as the sources update? How would you check its current status?
  3. If two sources disagreed about one of these facts, what would you need in order to trust one over the other?

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